The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same and, more particularly, to a nonvolatile semiconductor memory device a memory cell of which has a floating-gate electrode, a select-gate electrode, and a control-gate electrode, and a method of manufacturing the same.
In recent years, the integration degree of a nonvolatile semiconductor memory device, e.g., an EEPROM (Electrically Erasable and Programmable Read Only Memory), an EPROM (Erasable and Programmable Read Only Memory), and a flash EEPROM and has been increasing, and the memory cell has been micropatterned. As a memory cell occupying a small area, a "contactless array" in which the buried diffusion layers serve as bit lines and the respective cells do not form contacts with the bit lines has been realized.
Usually, the memory cell of a semiconductor memory device of this type has a multilayered gate structure consisting of source and drain regions formed on the surface of a substrate, a channel region provided between the source and drain regions, a floating-gate electrode formed on the channel region through the first gate insulating film, and a control-gate electrode formed on the floating-gate electrode through the second gate insulating film. In recent years, a memory cell in which a select-gate electrode is added to the multilayered gate structure has been proposed in order to increase the degree of freedom of operations, e.g., write, erase, and read, of the memory cell.
FIG. 5 shows the sectional portion of a nonvolatile semiconductor memory device, proposed by Japanese Patent Laid-Open No. 7-130884, to which a select-gate electrode is added. Referring to FIG. 5, reference numeral 201 denotes a p-type silicon substrate, 202, an n-type diffusion layer (drain); 203, an n-type diffusion layer (source); 204, a first gate oxide film; 205, a floating-gate electrode; 206, a second gate oxide film; 207, a select (transfer)-gate electrode; 208, a third gate oxide film; 209, a control-gate electrode; and 210, a protective film. In this memory cell, the floating-gate electrode 205 is formed as the side wall of the select-gate electrode 207, so that the area occupied by the floating-gate electrode 205 with respect to the memory cell can be decreased greatly.
The operation of the nonvolatile semiconductor memory device shown in FIG. 5 will be described. To perform a write operation, the p-type silicon substrate 201 is grounded, and 0 V, 1.5 V, 17 V, and 5 V are applied to the source 203, the select-gate electrode 207, the control-gate electrode 209, and the drain 202, respectively. Hot electrons are then generated below a portion near the interface between the select-gate electrode 207 and floating-gate electrode 205, and are injected to the floating-gate electrode 205, thereby performing the data write operation.
To erase data, the drain 202 and the control-gate electrode 209 are set to 14 V and 0 V, respectively, and the select-gate electrode 207 is opened. Then, electrons are emitted from the floating-gate electrode 205 to the drain 202 by the Fowler-Nordheim (to be abbreviated as FN hereinafter) tunnel current, thereby performing the erase operation.
To read data stored in the memory cell, 5 V, 1 V, 0 V, and 5 V are applied to the control-gate electrode (word line) 209, the drain (bit line) 202, the source 203, and the select-gate electrode 207, respectively, to select a specific memory cell. At this time, the current flowing between the source and drain changes depending on whether electrons are accumulated in the floating-gate electrode 205, so that data "0" or "1" can be determined.
In the conventional nonvolatile semiconductor memory device described above, since the floating-gate electrode is formed as the side wall of the select-gate electrode, the contact area through which the floating-gate electrode and control-gate electrode contact each other is small, and the coupling capacitance between the floating-gate electrode and control-gate electrode is small. For this reason, even when a high potential is applied to the control-gate electrode, the potential of the floating-gate electrode does not increase sufficiently. In the write and erase operations, electrons cannot be efficiently injected or emitted.
In the conventional case described above, when forming the floating-gate electrode, a polysilicon film must be etched back by anisotropic dry etching to form a polysilicon side wall to cover the two side surfaces of the select-gate electrode. Thereafter, the source-side polysilicon side wall must be masked with a resist and the source-side polysilicon side wall must be removed by etching. This prolongs the manufacturing process (mask step) and increases the manufacturing cost.